The disclosure relates generally to testing integrated circuit dies on wafers.
Wafers can contain many individual integrated circuit dies thereon. During the manufacturing process as part of the process, testing of the integrated circuit dies on a wafer is performed to detect defective integrated circuit dies on a wafer. One technique for performing wafer level testing is to contact each die with probes and a computer tester unit provides a set of patterns through the probes to each die. The test input stimulus can include functional and structural test patterns. The technique enables testing of all the dies on a wafer, but typically is done by probing each die individually one at a time. This can dramatically increase manufacturing time and cost and can wither die bumps that are used by the probes to make electrical contact with the die on the wafer.
Another proposal has been to include a wireless receiver and transmitter to communicate the test patterns and test results to provide contact list testing. However, such proposals employ a transmitter and receiver circuits in all of the dies on the wafer thus increasing the cost of each die.
A technique that attempts to reduce the wafer level test time is to use a multi-site testing approach wherein more than one die is simultaneously tested. This is typically done by the computer tester unit broadcasting the test stimulus, also referred to as input test data, to a specific subset of the die (8, 16 or 32 dies, for example) and comparing the outputs of all of these dies against the expected response. Such a multi-site testing technique typically requires broadcasting the stimulus to all of the dies simultaneously and comparing the responses of all the dies off-chip by the tester.
Accordingly, a need exists for an improved die structure, and testing system and method that addresses one or more of the above problems.